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ILX522K
2048 x 2pixel CCD Linear Sensor (Color) For the availability of this product, please contact the sales office.
Descriptions The ILX522K is a reduction type CCD linear sensor designed for color image scanner use. This sensor reads B4 size documents at a density of 200 DPI. (Dot Per Inch), and has 2lines analog memories to adjust the position of green line and red/blue line. A built-in timing generator and clockdrivers ensure direct drive at 5V logic. Features * Number of effective pixels: 2048 x 2pixels * Pixel size Red/Blue pixel: 14m x 12m (14m pitch) Green pixel: 14m x 14m (14m pitch) * Built-in timing generator, clock-drivers * Ultra-low lag * Good linearity * High sensitivity * Input Clock Pulse: CMOS 5V drive Absolute Maximum Ratings * Supply voltage VDD1 VDD2 Pin Configuration (Top View) 22 pin DIP (Cer-DIP)
Block Diagram
12 V1 11 V2
ROG
Driver
9
Driver
Driver
GND
11 6
V V
CCD analog shift register CCD analog shift register Analog memory Analog memory Readout gate G2047 G2048 D33 R1024 B1024 D33
Readout gate
Clock driver
Clock driver
RS VDD1
1 2
21 GND 20 VDD2 19 VGG 18 GND 17 NC
VOUT-R/B 3 VOUT-G 4 VDD1 5
NC 6 NC VDD1 ROG 7 8 9
16 CLK
Output amplifier Output amplifier Driver
14 GND
VOUT-R/B RS
GND 10 V2 11
G2047 R1024 G2048 B1024
13 VDD2 12 V1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
VOUT-G
VGG 19
3
1
4
E95436-PP
2
15 GND
VDD1
VDD2
20
GND
21
VDD1
5 D13 D13
GND
18
D32 G1 G2
D32 R1 B1
G1 G2
R1 B1
22 NC
CLK
16
VDD1
8
GND
10
VDD2
15
13 D46 D46
GND
14
ILX522K
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol RS VDD1 VOUT-R/B VOUT-G VDD1 NC NC VDD1 ROG GND V2 V1 VDD2 GND GND CLK NC GND VGG VDD2 GND NC Description Clock pulse input 9V power supply R/B signal out G signal out 9V power supply NC NC 9V power supply Clock pulse input GND Clock pulse input Clock pulse input 5V power supply GND GND Clock pulse input NC GND Output gate bias 5V power supply GND NC
Recommended Supply Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V
Note) Rules for raising and lowering power supply voltage. To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V). Clock Characteristics Item Input capacity of RS, CLK Input capacity of V1, V2 Input capacity of ROG Input clock frequency Symbol CRS, CCLK CV1, CV2 CROG fRS, fCLK Min. -- -- -- -- -2- Typ. 10 10 10 -- Max. -- -- -- 3.5 Unit pF pF pF MHz
ILX522K
Electrical Characteristics (Note 1) (Ta = 25C, VDD1 = 9V, VDD2 = 5V fRS = 3.5MHz Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Red Sensitivity Green Blue Sensitivity nonuniformity Saturation output voltage Dark voltage average Green Red/Blue Green Red/Blue Symbol RR RG RB PRNU VSAT VDRK-G VDRK-R/B DSNU-G DSNU-R/B IL IVDD1 IVDD2 TTE ZO VOS Min. 5.2 6.5 2.8 -- 1.0 -- -- -- -- -- -- -- 92.0 -- -- Typ. 8.0 10.0 4.3 5.0 1.5 0.3 1.5 0.6 2.0 0.02 20 16.0 98.0 150 5.4 Max. 10.8 13.5 5.8 15.0 -- 1.5 9.0 3.0 12.0 -- 40 32.0 -- -- -- % mA mA % V Note 6 -- -- -- -- Note 7 mV Note 5 % V Note 3 Note 4 V/(lx * s) Note 2 Unit Remarks
Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level
Note: 1) In accordance with the given electrooptical characteristics, the black level is defined as the average of D3, D4, to D10. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) PRNU is defined as indicated below in each color. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX - VMIN)/2 x 100 [%] VAVE
The maximum output of each color is set to VMAX, the minimum output to VMIN, and the average output to VAVE. 4) 5) 6) 7) Use below the minimum value of the saturation output voltage. Optical signal accumulated time int stands at 5ms. VOUT-G = 500mV (Typ.) VOS is defined as indicated below.
VOUT
VOS
GND
VOUT indicates VOUT-G and VOUT-R/B. -3-
Clock Timing Chart
5V
ROG
0V
5V
V1
0V
5V
V2
0V
2088 2094 1 2 3 0
5V
CLK
0
-4-
D1 D2 D3 D12 D13 D14 D30 D31 D32 G1 G2 D1 D2 D3 D12 D13 D14 D30 D31 D32 R1 B1
0V
5V
RS
0V
VOUT-G
D46 G2046 G2047 G2048 D33 D34 D39 D40
VOUT-R/B
D46 B1023 R1024 B1024 D33 D34 D39 D40
Optical Black (18 pixels) Dummy Signal (32 pixels) 1 Line Output (2094 pixels)
ILX522K
Note) CLK, RS pulses must have more than 2094 cycles.
ILX522K
ROG, V1, V2, CLK Timing
t6 ROG t1 V1
t7 t3 t4
t2
t6 t6 V2 t1 t2 t7 t3
t7
t5
CLK
Item ROG, V2 - CLK pulse timing ROG, V1, V2 pulse period ROG - V1 pulse timing V1 - CLK pulse timing ROG, V1, V2 pulse rise time, fall time
Symbol t1 t2, t4 t3 t5 t6, t7
Min. 1 28 1 1 0
Typ. 2 30 2 2 10
Max. -- -- -- -- 30
Unit s s s s ns
-5-
ILX522K
CLK, RS, VOUT Timing
CLK
t1
RS
t2
t3
t5
t4 VOUT
t6
Item CLK pulse high level period RS pulse high level period
Symbol t1 t2 t3
Min. 135 30 -- -- -- --
Typ. 500 250 60 25 70 25
Max. -- -- -- -- -- --
Unit ns ns ns ns ns ns
Signal output delay time
t4 t5 t6
These timing is the condition under fRS = 1MHz.
-6-
Application Circuit
CLK
V1
74HC04 0.01 10 16V
74HC04
9V
5V 21 20 19 18 17 16 15 14 12 13
22
NC
NC
VGG
VDD2
GND
GND
CLK
GND
GND
VDD2
RS
VDD1
VOUT-R/B
VOUT-G
VDD1
NC
1 2 3 7 4
5
6
NC
VDD1
ROG
8
9
10
GND
0.01 74HC04 1k 1k
V2
11
V1
-7-
0.01 74HC04 ROG VOUT-G 2SA1175 2SA1175 74HC04 V2 10 10V ILX522K Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
10 16V
RS
VOUT-R/B
ILX522K
Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8
Relative sensitivity
0.6
0.4
0.2
0 400
450
500
550 Wave length [nm]
600
650
700
Dark signal output temperature characteristics (Standard characteristics)
10 5
Output voltage rate
1 0.5
0.1
0
10
20
30
40
50
60
Ta - Ambient temperature [C]
Integration time output voltage characteristics (Standard characteristics)
Output voltage rate
1
0.5
0.1
1
5 int - integration time [ms]
10
-8-
ILX522K
Operational frequency characteristics of the VDD1 supply current (Standard characteristics)
40 Ta = 25C
Operational frequency characteristics of the VDD2 supply current (Standard characteristics)
20 Ta = 25C
IVDD1 - VDD1 supply current [mA]
30
IVDD2 - VDD2 supply current [mA]
15
20
10
10
5
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 fCLK - CLK clock frequency [MHz]
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 fCLK - CLK clock frequency [MHz]
Offset level vs. VDD1 characteristics (Standard characteristics)
9 8 Ta = 25C 7 7 9 8
Offset level vs. VDD2 characteristics (Standard characteristics)
Ta = 25C
VOS - Offset level [V]
6 5 4 3 2 1 0 8.5 9.0 VDD1 [V] 9.5 VOS VDD2 0.54
VOS - Offset level [V]
6 5 4 3 2 1 0 4.75 5 VDD2 [V] 5.25
Offset level vs. Temperature characteristics (Standard characteristics)
8
VOS - Offset level [V]
6
4
2
VOS Ta
-3mV/C
0 0 10 20 30 40 50 60 Ta - Ambient temperature [C]
-9-
ILX522K
Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DlP Packages The following points should be observed when handling and installing cer-DlP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39 N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29 N/surface (3) Tensile strength: 29 N/surface (4) Torsional strength: 0.9 Nm
Upper ceramic layer 39N 29N 29N 0.9Nm
Low-melting glass Lower ceramic layer (1) (2) (3) (4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.
- 10 -
ILX522K
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Since ILX522K has 2 line memory so that the signal of R/B line is delay, compese the optical system subscanning R/B line initially.
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Package Outline
Unit: mm
22pin DIP (400mil)
41.6 0.5 12
22
5.0 0.5
1 40.2
11
1. The height from the bottom to the sensor surface is 2.45 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
4.0 0.5
3.65
2.54 0.3
M
0.51
PACKAGE STRUCTURE
PACKAGE MATERIAL
Cer-DIP
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
ILX522K
PACKAGE WEIGHT
5.2g
4.45 0.5
(AT STAND OFF) 10.16
0.25
H
No.1 Pixel (Green)
10.0 0.5
V
9.0
0 to 9
6.26 0.8
28.672 (14m x 2048Pixels)
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